PX1500-4 – Xilinx Virtex-5 SXT FPGA DSP High-Speed Digitizer Board
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- Xilinx Virtex-5 FPGA Processing Option
- FIR Filtering or User Custom FPGA Processing Routines
- 4 Analog Input Channels up to 1.5 GS/s per Channel
- 2 Analog Input Channels up to 3 GS/s per Channel
- 8 Bits of Resolution
- Bandwidth up to 2 GHz
- 2 GB Total Onboard RAM for Sample Acquisition
- 1.4 GB/s Sustained PCIe Data Streaming Rate
- Windows Scope App and Complete C SDK Included
- Windows and Linux Operating Systems Supported
The FPGA processing model version, the PX1500-4-SP95, features an onboard upgraded secondary Xilinx Virtex-5 SX95T FPGA for embedded signal processing on channels 3 and 4 inputs. This processing FPGA then conducts both the data acquisition operation of these channel inputs in addition to the targeted processing routine on the acquired data.
When FPGA processing is enabled, the targeted signal processing routine is conducted and the resulting processed data output is then transferred back to the System FPGA, which can then stream the resulting data to the host PC system via the PCIe interface with PCIe Buffered Acquisition mode.
PX1500-4-SP95 FPGA processing models include the following signal processing routines:
- Finite Impulse Response (FIR) Filtering – Provides programmable FIR filtering for channel 3 and channel 4 inputs with the ability to load filter coefficients from a file source for each channel.
The PX1500 Scope App includes an interface to enable FPGA processing and for making settings that apply to the routine.
The processing FPGA is fully end user programmable, allowing for customized embedded processing routines to be developed and utilized with the PX1500-4-SP95. Signatec provides custom FPGA design services to meet specific application requirements for customers who don’t want to program the FPGA themselves. Contact Signatec to discuss specific project requirements, feasibility, and scope for customized solutions.
Alternatively, the optional PX1500 FPGA Development Kit is provided for customers who want to develop their own embedded processing routines.
The Signatec PX1500 FPGA Development Kit requires the end user to have the Xilinx ISE Design Suite software sold directly by Xilinx and provides the native VHDL source code project of the existing PX1500 FPGA processing routines for FIR Filtering. This VHDL source code project serves to demonstrate how to write real-time embedded signal processing routines for the onboard Xilinx FPGA device with its defined interfaces for utilizing the various FIFO, RAM, processing elements, and bus interface resources.
Purchase of the PX1500 FPGA Development Kit includes up to 5 hours of DynamicSignals engineering support. Additional hours of support can be purchased in units of 5-Hour Block Packages.
The custom programmable FPGA logic needs to manage two data interfaces: the acquisition data interface and the user register interface. The acquisition data interface provides data from the PX1500 acquisition circuits to be processed by the user logic in the programmable FPGA. The register interface provides a way for user defined custom parameters to be dynamically set by the host PC system application.
The PX1500 Scope App includes a generic FPGA Processing interface for enabling FPGA processing and to read/write to specific registers for working with the custom user logic in the FPGA. For custom application software development, standard C functions are provided for interfacing with the FPGA registers.
Developed custom user logic firmware is packaged and uploaded to the PX1500-4-SP95 through its PCIe interface to the host PC utilizing the PX1500 Scope App. Alternatively the custom user logic firmware can also be directly loaded through the PX1500-4-SP95 JTAG header utilizing a Xilinx JTAG programmer sold directly by Xilinx.
The PX1500-4 is a four channel waveform capture board that can acquire up to 1.5 GS/s on each channel, or up to 3 GS/s for dual channel operation when ADC data is interleaved. The PX1500-4 analog front end is hardware configured to use either a transformer coupled front end or an amplifier connection. The transformer connection can only be set for an AC-coupled input configuration and has a signal frequency capture range of 5 MHz to 2 GHz. The amplifier connection can be set for either AC or DC-coupled input configuration with a signal frequency capture range up to 1 GHz.
The PX1500-4 is designed to maximize the quality of the captured signal in terms of signal-to-noise ratio and spurious-free dynamic range over a very wide frequency range. For this reason, there are no switch components in the analog signal path or bandwidth limiting programmable gain amplifiers; giving customers the benefit of a nearly direct path to the ADC from either the amplifier or transformer coupled input.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 200 MHz to 1.5 GHz, offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, ±5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
The PX1500-4 has a total of 2 GB memory for onboard sample data storage. Alternatively, PCIe Buffered Acquisition mode utilizes the onboard RAM as a FIFO to provide non-stop continuous acquisition and streaming of sample data to the host PC via the PCIe interface. With PCIe Buffered Acquisition mode, the PX1500-4 can sustain up to a maximum 1.4 GB/s data streaming rate over its PCIe Gen1 x8 interface to the host PC for real-time high-speed processing and/or data recordings.
The PX1500-4 also provides an option for an upgraded secondary Xilinx Virtex-5 SX95T FPGA for embedded signal processing on channels 3 and 4 inputs. FPGA processing models of the PX1500-4 include a FIR Filtering feature standard for these inputs. The processing FPGA is fully end user programmable, allowing for custom developed embedded processing routines.
Up to five PX1500-4 digitizers can be setup for synchronous acquisition operations for a total of 20 input channels by utilizing the separate Signatec SYNC1500 clock/trigger driver source card.
A Windows oscilloscope program, the PX1500 Scope App, allows the operator to view/edit all digitizer hardware settings as well as record and display acquisition data. It is included along with a full complete C SDK for custom application development.
PX1500-4 Full Data Sheet
Update: Revision 1.10 - 08/31/2015
File Size: 669 KB
|External Signal Connections|
|Analog Inputs (4):||SMA|
|Digital Input / Output:||SMA|
|Analog Inputs – Amplifier Front End|
|Full Scale Voltage Range:||500mV peak-peak|
|Bandwidth:||1 MHz to 1 GHz (AC-Coupled)
DC to 1 GHz (DC-Coupled)
|SNR (dc-500 MHz):||42 dB|
|SFDR (1-500 MHz):||53 dB|
|Analog Inputs – Transformer Front End|
|Full Scale Input Voltage Range:||700mV peak-peak|
|Bandwidth:||5 MHz to 2 GHz (AC-Coupled)|
| SNR (dc-500 MHz):
(@ 1000 MHz):
(@ 1500 MHz):
| SFDR (5-1000 MHz):
(@ 1500 MHz):
|Signal Type:||LVPECL (3.3V Logic)|
|Impedance:||50 ohms to +1.3V|
|Internal Synthesized Clock|
|Frequency Range:||200 MHz to 1.5 GHz|
|Resolution:||better than ±62.5 PPM|
|Accuracy:||better than ±5 PPM|
|Signal Type:||sine wave or square wave|
|Termination:||Ground or +1.3V|
|Frequency:||200 MHz to 1.5 GHz|
|Clock Dividers:||1 to 7|
|Post ADC Clock Divider|
|Divider Settings:||1, 2, 4, 8, 16, 32|
|Internal:||10 MHz, ±5 PPM max.|
|External:||10 MHz, ±50 PPM max (required for lock)|
|Digital Input / Output|
|Type:||TTL Logic Level (standard)|
|Max. Frequency:||200 MHz|
|Connection:||100 ohms to FPGA I/O|
|Output Modes:||0V, Synchronized Trigger, ADC Clock ÷ 2, 3.3V|
|Input Modes:||Digital pulse for timestamp request|
|Post Trigger:||single start trigger fills active memory|
|Segmented:||start trigger for each memory segment|
|Pre-trigger Samples:||samples prior to trigger are stored; 16k max.; total all channels|
|Trigger Delay Samples:||delay from trigger to data storage; Up to 64k digitizer clock cycles max.|
|Total Size:||2 GB|
|Segment Size:||Up to 512 Megasamples|
|Segment Re-Arm Time:||150 nanoseconds|
|Addressing:||DMA transfers from starting address|
|+3.3V:||3.3 Amps max.|
|+12V:||1.0 Amps max.|
|Absolute Maximum Ratings|
|Trigger Input:||-0.2V to +4V DC|
|Clock Input:||5V peak-to-peak|
|Operating Temperature:||+32 to +122F / 0 to +50C|
|Storage Temperature:||-4 to +158F / -20 to +70C|
|Operating Relative Humidity:||10% to 90%, non-condensing|
|Operating Vibration:||0.25 G, 5 Hz to 500 Hz|
|Operating Shock:||2.5 G, 11 ms, 1/2 sine|
|Board Dimensions:||7.5" L x 4.3" H x 0.75" W /
190.5 mm L x 109.22 mm H x 19.05 mm W
|Regulatory Information:||RoHS Compliant|