PX14400D-SP – Xilinx Virtex-5 SXT FPGA DSP DC Coupled High-Speed Digitizer Board
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- Customizable Xilinx Virtex-5 SXT FPGA DSP
- Virtex-5 SX50T FPGA option provides 52,224 logic cells / 4,752 kbits block RAM / 288 DSP slices
- Virtex-5 SX95T FPGA option provides 94,208 logic cells / 8,784 kbits block RAM / 640 DSP slices
- FPGA DSP Packages with Fixed Capabilities for FFT, FIR Filtering, DDC Real-Time Processing
- FPGA DSP Packages with Programmable Capabilities to allow for User Implementation of Custom In-Line DSP
- 512 MB Onboard RAM for Dedicated FPGA Processing Option
- Up to 400 MHz Sample Rate per Channel
- 14 Bits of Resolution
- 2 DC-Coupled Analog Input Channels
- Bandwidth from DC to 200 MHz
- 512 MB Onboard RAM for Sample Acquisition
- 1.4 GB/s Sustained PCIe Data Streaming Rate
- Windows Scope App and Complete C SDK Included
- Windows and Linux Operating Systems Supported
The FPGA processing model versions of the PX14400D feature an onboard secondary Xilinx Virtex-5 SX50T or SX95T FPGA with its own 512 MB RAM bank for dedicated embedded signal processing.
When FPGA processing is enabled, acquired data is transferred from the System FPGA to the Signal Processing FPGA where the targeted signal processing routine is conducted. The resulting processed data output is then transferred back to the System FPGA, which can then stream the resulting data to the host PC system via the PCIe interface with PCIe Buffered Acquisition mode.
PX14400D FPGA processing models include the following signal processing routines:
- Programmable Decimation and Down Conversion (DDC) – This is the default enabled processing feature on PX14400D FPGA processing models. It provides decimation processing for single channel mode only with decimation factors of 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, and 8192 for a specified NCO frequency.
- Fast Fourier Transform (FFT) – Performs programmable zero padding of the data to 1k or 2k samples, Blackman Harris and Rectangular windowing, 1k or 2k FFTs, optional magnitude square calculation in dB, interleaving of FFT block of data with the raw block of data, and also allows for a programmable window function for single channel mode only.
- Finite Impulse Response (FIR) Filtering – Provides programmable FIR filtering for one or two channels with the ability to load filter coefficients from a file source for each channel.
Any of these provided FPGA processing routines can be loaded onto the PX14400D with the PX14400 Scope App, which also detects the current loaded processing feature and displays the related interface for making settings that apply to the routine.
The processing FPGA is fully end user programmable, allowing for customized embedded processing routines to be developed and utilized with the PX14400D. Signatec provides custom FPGA design services to meet specific application requirements for customers who don't want to program the FPGA themselves. Contact Signatec to discuss specific project requirements, feasibility, and scope for customized solutions.
Alternatively, the optional PX14400 FPGA Development Kit is provided for customers who want to develop their own embedded processing routines. The FPGA Development Kit requires the end user to have the Xilinx ISE Design Suite software sold directly by Xilinx and provides native VHDL source code projects to demonstrate how to write real-time embedded signal processing routines for the onboard Xilinx FPGA device with its defined interfaces for utilizing the various FIFO, RAM, processing elements, and bus interface resources. Purchase of the PX14400 FPGA Development Kit includes up to 5 hours of DynamicSignals engineering support. Additional hours of support can be purchased in units of 5-Hour Block Packages.
There are two PX14400D FPGA processing models that provide the following raw FPGA resources:
- PX14400D-SP50 = Virtex-5 SX50T: 52,224 logic cells / 4,752 kbits block RAM / 288 DSP slices.
- PX14400D-SP95 = Virtex-5 SX95T: 94,208 logic cells / 8,784 kbits block RAM / 640 DSP slices.
The custom programmable FPGA logic needs to manage two data interfaces: the acquisition data interface and the user register interface. The acquisition data interface provides data from the PX14400D acquisition circuits to be processed by the user logic in the programmable FPGA. The register interface provides a way for user defined custom parameters to be dynamically set by the host PC system application.
The PX14400 Scope App includes a generic FPGA Processing interface for enabling FPGA processing and to read/write to specific registers for working with the custom user logic in the FPGA. For custom application software development, standard C functions are provided for interfacing with the FPGA registers.
Developed custom user logic firmware is packaged and uploaded to the PX14400D through its PCIe interface to the host PC utilizing the PX14400 Scope App. Alternatively the custom user logic firmware can also be directly loaded through the PX14400D JTAG header utilizing a Xilinx JTAG programmer sold directly by Xilinx.
The PX14400D is a dual channel DC-coupled waveform capture board that can acquire up to 400 MS/s on each channel with 14-bit resolution. (For AC-coupled requirements, refer to PX14400A product model.) The PX14400D analog front end has a signal frequency capture range of DC to 200 MHz with 3-pole Bessel filters on each input channel.
The PX14400D has two software selectable input voltage ranges of 400mV and 1.2V peak-to-peak. Optional inline SMA attenuators are available for changing these levels if needed; for example, the use of 6 dB attenuators effectively change the input levels to 800mV and 2.4V peak-to-peak. Alternatively, please refer to the separate PX14400D2 product model that provides six software selectable input ranges of 200mV, 333mV, 600mV, 1V, 1.6V, and 3V with various bandwidth specifications at each of these input ranges.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 20 MHz to 400 MHz (except for an un-settable range of 277 MHz to 308 MHz), offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, ±5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
The PX14400D has a primary sample-data RAM bank of 512 MB memory for onboard sample data storage. Alternatively, PCIe Buffered Acquisition mode utilizes the onboard RAM as a FIFO to provide non-stop continuous acquisition and streaming of sample data to the host PC via the PCIe interface. With PCIe Buffered Acquisition mode, the PX14400D can sustain up to a maximum 1.4 GB/s data streaming rate over its PCIe Gen1 x8 interface to the host PC for real-time high-speed processing and/or data recordings.
Up to five PX14400D digitizers can be setup for synchronous acquisition operations for a total of 10 input channels by utilizing the separate Signatec SYNC1500 clock/trigger driver source card.
A Windows oscilloscope program, the PX14400 Scope App, allows the operator to view/edit all digitizer hardware settings as well as record and display acquisition data. It is included along with a full complete C SDK for custom application development.
PX14400D (DC-Coupled) Full Data Sheet
Update: Revision 1.3 - 08/24/2015
File Size: 698 KB
|External Signal Connections|
|Analog Input, Channel 1:||SMA|
|Analog Input, Channel 2:||SMA|
|Digital Input / Output:||SMA|
|Full Scale Voltage Ranges:||400mV and 1.2V peak-to-peak|
|Bandwidth:||DC - 200 MHz (Bessel filter)|
|SNR (1-200 MHz):||67 dB|
|SFDR (@ 25 MHz):||80 dB|
|SFDR (@ 100 MHz):||73 dB|
|Signal Type:||digital, LVCMOS signal level|
|Internal Synthesized Clock|
|Frequency Range:||20 MHz to 400 MHz|
|Unsettable Ranges:||277 MHz to 308 MHz|
|Resolution:||better than ±10 PPM|
|Accuracy:||better than ±5 PPM|
|Signal Type:||sine wave or square wave|
|Frequency:||20 MHz to 400 MHz|
|Amplitude:||100mV to 2.0V peak-peak|
|Clock Dividers:||1 to 20|
|Post ADC Clock Divider|
|Divider Settings:||1, 2, 4, 8, 16, 32|
|Internal:||10.0 MHz, ±5 PPM max.|
|External:||10.0 MHz, ±50 PPM max (required for lock)|
|Digital Input / Output|
|Type:||TTL Logic Level (standard)|
|Max. Frequency:||200 MHz|
|Connection:||50 ohms to FPGA I/O|
|Output Modes:||0V, Synchronized Trigger, ADC Clock ÷ 2, 3.3V|
|Input Modes:||Digital pulse for timestamp request|
|Post Trigger:||single start trigger fills active memory|
|Segmented:||start trigger for each memory segment|
|Pre-trigger Samples:||samples prior to trigger are stored; Single Channel: 8k max.; Dual Channel: 4k max per channel|
|Trigger Delay Samples:||delay from trigger to data storage; Up to 64k digitizer clock cycles|
|Total Size for Acquisition:||256 Megasamples (512 MB)|
|Segment Size:||Up to 128 Megasamples|
|Segment Re-Arm Time:||150 nanoseconds|
|Addressing:||DMA transfers from starting address|
|+3.3V:||3.3 Amps max.|
|+12V:||1.0 Amps max.|
|Absolute Maximum Ratings|
|Trigger Input:||-0.2V to +4V DC|
|Clock Input:||5V peak-to-peak|
|Operating Temperature:||+32 to +122F / 0 to +50C|
|Storage Temperature:||-4 to +158F / -20 to +70C|
|Operating Relative Humidity:||10% to 90%, non-condensing|
|Operating Vibration:||0.25 G, 5 Hz to 500 Hz|
|Operating Shock:||2.5 G, 11 ms, 1/2 sine|
|Board Dimensions:||7.5" L x 4.3" H x 0.75" W /
190.5 mm L x 109.22 mm H x 19.05 mm W